In semiconductor components comprising a logic circuit such as is used as a central processing unit (CPU), for example, standard cells comprising p-channel transistors are arranged in a well doped in n-conducting fashion. These n-doped wells are fixedly connected to the highest electrical potential provided (supply voltage VDD). What is achieved thereby is that the pn-junction between the well doped in n-conducting fashion and the source region becomes non-conducting. In addition, defined transistor properties are obtained. Moreover, this prevents the well potential from decreasing below a value at which a so-called latch-up of the component occurs, the latch-up having the effect that the component is no longer functional.
One problem in the case of semiconductor components is a required safeguarding against light attacks which can bring about functional disturbances of the component or are intended to enable an undesirable external analysis of the circuit construction. There are already a series of proposals as to how a semiconductor component can be protected against light attacks. However, the necessary measures are generally very complicated and therefore make the component considerably more expensive. Moreover, the additional area requirement of the components of a protection circuit easily exceeds the available area for the entire integrated circuit. The known measures relate without exception to global light attacks, that is to say light attacks that are not restricted to delimited regions. No efficient measures are known against local light attacks.